Jitter Suppression Techniques for High-Speed Sample-and-Hold Circuits-Reference-Cited by-同舟云学术

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Jitter Suppression Techniques for High-Speed Sample-and-Hold Circuits

Published:2020-01 Issue:1 Volume:67 Page:1-11
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Jamali-Zavareh Shiva^ORCID,Harjani Ramesh^ORCID

Funder

Defense Advanced Research Projects Agency

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/8952842/08931729.pdf?arnumber=8931729

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Low Spur 5.9-GHz CMOS Frequency Synthesizer with Loop Sampling Filter for C-V2X Applications;Journal of Circuits, Systems and Computers;2023-03-01

2. Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk;Integration;2023-01

3. ADC Clock Jitter Measurement Based on Simple Coherent Sampling Algorithm;Journal of Physics: Conference Series;2022-11-01

4. Small-Signal Processing Low-Overhead Operational Amplifier for delta-Sigma ADC;Journal of Circuits, Systems and Computers;2022-07-18

5. A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS;Circuits, Systems, and Signal Processing;2021-01-21

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