A Framework for Neural Network Inference on FPGA-Centric SmartNICs
Author:
Affiliation:
1. Boston University,ECE Department,Boston,MA
2. University of Rochester,ECE Department,Rochester,NY
3. Pacific Northwest National Laboratory,Richland,WA
4. Microsoft,Redmond,WA
5. Rice University,Houston,TX
Funder
Compute-Flow-Architecture (CFA) project under PNNL's Data-Model-Convergence (DMC) LDRD Initiative
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10035104/10035106/10035214.pdf?arnumber=10035214
Reference47 articles.
1. Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware
2. A Reconfigurable Compute-in-the-Network FPGA Assistant for High-Level Collective Support with Distributed Matrix Multiply Case Study
3. Azure Accelerated Networking: SmartNICs in the Public Cloud;Firestone
4. Distributed Recommendation Inference on FPGA Clusters
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1. SmartFuse: Reconfigurable Smart Switches to Accelerate Fused Collectives in HPC Applications;Proceedings of the 38th ACM International Conference on Supercomputing;2024-05-30
2. Performance Evaluation of VirtIO Device Drivers for Host-FPGA PCIe Communication;2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2024-05-27
3. Software-Hardware Co-design of Heterogeneous SmartNIC System for Recommendation Models Inference and Training;Proceedings of the 37th International Conference on Supercomputing;2023-06-21
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