28.1 A Fully Integrated, Domino-Like-Buffered Analog LDO Achieving –28dB Worst-Case Power-Supply Rejection Across the Frequency Spectrum from 10Hz to 1GHz with 50pF On-Chip Capacitance
Author:
Affiliation:
1. Korea Advanced Institute of Science and Technology,Daejeon,Korea
2. Electronics and Telecommunications Research Institute,Daejeon,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454478.pdf?arnumber=10454478
Reference6 articles.
1. A 0.5–1 V, −68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS
2. An Output-Capacitorless Analog LDO Featuring Frequency Compensation of Four-Stage Amplifier
3. An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique
4. An Adaptively Biased Output-Capacitor-Free Low-Dropout Regulator With Supply Ripple Subtraction and Pole-Tracking-Compensation
5. 17.11 A 0.65ns-response-time 3.01ps FOM fully-integrated low-dropout regulator with full-spectrum power-supply-rejection for wideband communication systems
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1. A power-efficient fast-transient OCL-LDO with adaptive super source follower and active capacitor compensation management;Microelectronics Journal;2024-09
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