10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm
Author:
Affiliation:
1. Korea Advanced Institute of Science and Technology,Daejeon,Korea
2. Seoul National University,Seoul,Korea
Funder
Samsung
IC Design Education Center
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454495.pdf?arnumber=10454495
Reference7 articles.
1. 32.6 A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS
2. A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
3. 32.1 A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM
4. A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching
5. A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs
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1. A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning;Electronics;2024-07-05
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