A Parallel Acceleration Technique based on Bordered Block Diagonal Matrix Reordering for Exponential Integrator Method-Reference-Cited by-同舟云学术

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A Parallel Acceleration Technique based on Bordered Block Diagonal Matrix Reordering for Exponential Integrator Method

Published:2024-05-10 Issue: Volume:26 Page:94-99
ISSN:
Container-title:2024 2nd International Symposium of Electronics Design Automation (ISEDA)
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Author:

Zhou Hang¹,Yang Dongen¹,Lin Yangfei¹,Dai Yong¹,Chen Quan¹

Affiliation:

1. School of Microelectronics, Southern University of Science and Technology,ShenZhen,China,518055

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10616249/10617469/10617631.pdf?arnumber=10617631

Reference20 articles.

1. A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation

2. Circuit simulation via matrix exponential method for stiffness handling and parallel pro-cessing;Weng

3. Power grid simulation using matrix exponential method with rational Krylov subspaces

4. Algorithm 907

5. An overview of SuperLU

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