Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST-Reference-Cited by-同舟云学术

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Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST

Published:2010-04 Issue: Volume: Page:
ISSN:
Container-title:2010 28th VLSI Test Symposium (VTS)
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Author:

Ahmed Fahad,Milor Linda

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5464131/5469528/05469614.pdf?arnumber=5469614

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. SRAM Gauge: SRAM Health Monitoring via Cells Race;2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED);2021-07-26

2. PVTA-Aware Performance SRAM Sensor for IoT Applications;INCREaSE 2019;2019-09-20

3. $In~Situ$ and In-Field Technique for Monitoring and Decelerating NBTI in 6T-SRAM Register Files;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-11

4. Self-Test and Diagnosis for Self-Aware Systems;IEEE Design & Test;2018-10

5. Bias-Induced Healing of $V_{\text {min}}$ Failures in Advanced SRAM Arrays;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-02

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