High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models-Reference-Cited by-同舟云学术

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High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models

Published:1996 Issue:9 Volume:15 Page:1106-1118
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Qing Zhu ,Dai W.W.M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx1/43/11446/00536716.pdf?arnumber=536716

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