32.6 A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS-Reference-Cited by-同舟云学术

32.6 A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS

Published:2021-02-13 Issue: Volume: Page:
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Container-title:2021 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Thaller Edwin,Levinger Run,Shumaker Evgeny,Farber Aryeh,Bershansky Sergey,Geron Nir,Ravi Ashoke,Banin Rotem,Kadry Jasmin,Horovitz Gil,Krassnitzer Christian,Duller Christoph,Torta Patrick,Elzinga Mark,Azadet Kamran

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9365732/9365735/09365775.pdf?arnumber=9365775

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