11.8 An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS-Reference-Cited by-同舟云学术

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11.8 An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS

Published:2021-02-13 Issue: Volume: Page:
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Container-title:2021 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Farjadrad Ramin,Kaviani Kambiz,Nguyen David,Brown Michael,Geelen Govert,Bastiaansen Corne,Rao Narendra,Popuri Viswa,Shen Greg,Khatibi Hamid,Dey Saudas,Chatterjee Anirban,Shen David,Zijlstra Peter,Gunnink Harrie,Zhang Kebin,Penumuchu Venkat,Weiss Oliver,Paulus Edward,Briaire Joost

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9365732/9365735/09365852.pdf?arnumber=9365852

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation;IEEE Journal of Solid-State Circuits;2024-08

3. Energy Efficient Resistor-Transconductor Hybrid-Based Full-Duplex Transceiver for Serial Link;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

4. A 56-Gb/S,0.708pj/Bit Single-Ended Simultaneous Bidirectional Transceiver with Hybrid Errors Cancellation Techniques for Die-to-Die Interface;2024

5. A Pattern Cancel DAC system design methodology for FMCW radar;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24

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