A 28nm 6GHz 2b Continuous-Time $\Delta\Sigma$ ADC with −101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction-Reference-Cited by-同舟云学术

A 28nm 6GHz 2b Continuous-Time $\Delta\Sigma$ ADC with −101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction

Published:2022-02-20 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Bolatkale Muhammed¹,Rutten Robert¹,Brekelmans Hans¹,Bajoria Shagun¹,Gao Yihan¹,Burdiek Bernard²,Breems Lucien¹

Affiliation:

1. NXP Semiconductors,Eindhoven,The Netherlands

2. NXP Semiconductors,Hamburg,Germany

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731602.pdf?arnumber=9731602

Reference6 articles.

1. A 5GS/s 156MHz BW 70dB DR continuous-time sigma-dnltamodulator with time-interleaved reference data-weighted averaging;dayanik;IEEE Symposium on VLSICircuits,2017

2. 20.7 A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ

3. Wideband UHF ISM-band transceiver supporting multichannel reception and DSSS modulation

4. A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique

5. A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR

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