33.4 A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference-Reference-Cited by-同舟云学术

33.4 A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Cai Hao¹,Bian Zhongjian¹,Hou Yaoru¹,Zhou Yongliang¹,Cui Jia-le¹,Guo Yanan¹,Tian Xiaoyun¹,Liu Bo¹,Si Xin¹,Wang Zhen²,Yang Jun¹,Shan Weiwei¹

Affiliation:

1. Southeast University,Nanjing,China

2. Nanjing Prochip Electronic Technology,Nanjing,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067339.pdf?arnumber=10067339

Reference7 articles.

1. Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS

2. A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations

3. A crossbar array of magnetoresistive memory devices for in-memory computing

4. A 22nm 128-kb MRAM Row/Column-Parallel In-Memory Computing Macro with Memory-Resistance Boosting and Multi-Column ADC Readout

5. A 22nm 1 Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices;chang;ISSCC,2020

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