6.8 A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing $\mathbf{3+1}$ Hybrid FFE Taps in 40nm
Author:
Affiliation:
1. Hanyang University,Seoul,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067452.pdf?arnumber=10067452
Reference6 articles.
1. 8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS
2. An 8b DAC-Based SST TX Using Metal Gate Resistors with 1. 4pJ/b Efficiency at 112Gb/s PAM-4 and B-Tap FFE in 7nm CMOS;kossel;ISSCC,2021
3. A 32-Gb/s High-Swing PAM-4 Current-Mode Driver with Current-Bleeding Cascode Technique and Capacitive-Coupled Pre-drivers in 40-nm CMOS for Short-Reach Wireline Communications
4. 6.8 A 100Gb/s NRZ Transmitter with 8-Tap FFE Using a 7b DAC in 40nm CMOS
5. 8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS
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1. An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation;IEEE Journal of Solid-State Circuits;2024-08
2. A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-06
3. Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21
4. A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization;IEEE Journal of Solid-State Circuits;2024-01
5. A Single-Ended Duobinary-PAM4 (PAM7) Transmitter With a 2-Tap Feed-Forward Equalizer;IEEE Solid-State Circuits Letters;2023
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