Study on Single Event Burnout Effect for 18V LDMOS Based on 0.18µm Process Technology
Author:
Affiliation:
1. State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China,Chengdu,China
2. Beijing Microelectronics Technology Institute,Beijing,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10090225/10090247/10090399.pdf?arnumber=10090399
Reference8 articles.
1. Transmission Line Pulse Test Method for Estimating SEB Performance of $n$ -Channel Lateral DMOS Power Transistors
2. Single event burnout as the failure mode for a low voltage MOSFET driver
3. Single-Event Burnout and Avalanche Characteristics of Power DMOSFETs
4. Simulating single-event burnout of n-channel power MOSFET's
5. Impact of Ion Energy and Species on Single Event Effects Analysis
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Source Segmented LDMOS Structure for Improving Single Event Burnout Tolerance Based on High-Voltage BCD Process;IEEE Transactions on Device and Materials Reliability;2024-03
2. Improvement of reverse conduction characteristic and single event effect for a novel vertical GaN field effect transistor with an integrated MOS-channel diode;Microelectronics Journal;2024-02
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