A Unified Parallel CORDIC-Based Hardware Architecture for LSTM Network Acceleration
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA
Funder
National Science Foundation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software
Link
https://ieeexplore.ieee.org/ielam/12/10243393/10105468-aam.pdf
Reference42 articles.
1. The CORDIC Trigonometric Computing Technique
2. YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration
3. Real-time FPGA-Based Outlier Detection using Autoencoder and LSTM
4. XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference
5. Expanding the range of convergence of the CORDIC algorithm
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