75 nm damascene metal gate and high-k integration for advanced CMOS devices-Reference-Cited by-同舟云学术

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75 nm damascene metal gate and high-k integration for advanced CMOS devices

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Container-title:Digest. International Electron Devices Meeting,
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Author:

Guillaumot B.,Garros X.,Lime F.,Oshima K.,Tavel B.,Chroboczek J.A.,Masson P.,Truche R.,Papon A.M.,Martin F.,Damlencourt J.F.,Maitrejean S.,Rivoire M.,Leroux C.,Cristoloveanu S.,Ghibaudo G.,Autran J.L.,Skotnicki T.,Deleonibus S.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/8330/25999/01175851.pdf?arnumber=1175851

Cited by 95 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Gate C-V Characteristics of n-Channel MOSFET Considering Quantum Mechanical Effects;2023 International Conference on Smart Systems for applications in Electrical Sciences (ICSSES);2023-07-07

2. Investigation of electrical/analog performance and reliability of gate metal and source pocket engineered DG-TFET;Microsystem Technologies;2020-04-18

3. Increasing I ON / I OFF by embedding a low doped buried layer in the channel of a dual‐material double‐gate junctionless MOSFET;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2019-08-14

4. Carrier scattering in high-κ/metal gate stacks;Journal of Applied Physics;2017-03-21

5. A two-dimensional (2D) analytical surface potential and subthreshold current model for underlap dual-material double-gate (DMDG) FinFET;Journal of Computational Electronics;2016-08-26

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