ATPG for Delay Defects in Current Mode Threshold Logic Circuits
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Published:2016-11
Issue:11
Volume:35
Page:1903-1913
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ISSN:0278-0070
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Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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language:
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Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.
Author:
Palaniswamy Ashok Kumar,Tragoudas Spyros,Haniotakis Themistoklis
Funder
National Science Foundation I/UCRC for Embedded Systems at Southern Illinois University Carbondale
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
1 articles.
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1. A Simple and Effective Heuristic Method for Threshold Logic Identification;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017