Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip-Reference-Cited by-同舟云学术

Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip

Published:2016-04 Issue:4 Volume:35 Page:623-636
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Beneventi Francesco,Bartolini Andrea,Vivet Pascal,Benini Luca

Funder

FP7 ERC Advance Project MULTITHERMAN

H2020 FETHPC ExaNoDe

H2020 FETHPC ANTAREX

YINS RTD Project evaluated by the Swiss National Science Foundation and funded by Nano-Tera.ch with Swiss Confederation financing

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

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