Implementation of Unbiased Rounding for 64-Bit Floating Point Adder-Reference-Cited by-同舟云学术

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Implementation of Unbiased Rounding for 64-Bit Floating Point Adder

Published:2022-12-28 Issue: Volume: Page:
ISSN:
Container-title:2022 International Conference on Recent Trends in Microelectronics, Automation, Computing and Communications Systems (ICMACC)
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Author:

Dasu Vani¹,Ragini K.¹

Affiliation:

1. G. Narayanamma Institute of Technology and Science,Department of Electronics and Communication Engineering,Hyderabad,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10093234/10093245/10093518.pdf?arnumber=10093518

Reference20 articles.

1. Performing Arithmetic Operations on Round-to-Nearest Representations;ercegovac;Digital Arithmetic,2003

2. HUB Floating-point Addition Using Unbiased Rounding;shaik;IOSR Journal of VLSI and Signal Processing (IOSR-JVSP),2020

3. Leading-zero anticipatory logic for high-speed floating point addition

4. Comparative Analysis of 32 bit carry lookahead adder using high speed constant delay logic;rao;IJSETR International Journal of Science Engineering and Technology Research,2014

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