A novel edge termination for high voltage SiC devices
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7509008/7520753/07520818.pdf?arnumber=7520818
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Experimental Demonstration of the Double-Trench, Buried-P JTE Edge Termination with Short Edge Width and High dV/dt Capability for 1200 V-class SiC Devices;2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD);2024-06-02
2. Demonstration of a simple and efficient design methodology for high‐voltage floating field limiting ring in SiC power devices;Electronics Letters;2024-05
3. A High Efficiency Composite Junction Termination for SiC Power Devices;2023 20th China International Forum on Solid State Lighting & 2023 9th International Forum on Wide Bandgap Semiconductors (SSLCHINA: IFWS);2023-11-27
4. Termination Design of 6.5kV SiC MOSFET with Epitaxial Current Spreading Layer;2023 20th China International Forum on Solid State Lighting & 2023 9th International Forum on Wide Bandgap Semiconductors (SSLCHINA: IFWS);2023-11-27
5. Simulation of gradient floating field limiting rings for 4H-SiC power devices;Journal of Physics: Conference Series;2022-07-01
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