A Novel Circuit and Layout Design of SEU Tolerant SRAM in a 65nm CMOS Process
Author:
Affiliation:
1. Northwestern Polytechnic University,School of Computer Science,Xi'an,China
2. Xi'an Branch of China Academy of Space Technology,Xi'an,China
Funder
Fundamental Research Funds for the Central Universities
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10241359/10241362/10241793.pdf?arnumber=10241793
Reference11 articles.
1. Multiple Bit Upsets and Error Mitigation in Ultra-Deep Submicron SRAMS
2. Extrapolation Method of On-Orbit Soft Error Rates of EDAC SRAM Devices From Accelerator-Based Tests
3. Embedded-memory test and repair: infrastructure IP for SoC yield
4. Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering
5. Investigation of Increased Multi-Bit Failure Rate Due to Neutron Induced SEU in Advanced Embedded SRAMs
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