10GS/s 10bit Time-interleaved SAR ADC in 28nm CMOS
Author:
Affiliation:
1. University of Chinese Academy of Science Institute of Microelectronics Chinese Academy of Science,School of Integrated Circuits,Beijing,China,100049
2. Institute of Microelectronics Chinese Academy of Science,Beijing,China,100029
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10365709/10365561/10365895.pdf?arnumber=10365895
Reference12 articles.
1. A 0.014mm2 10-bit 2GS/s time-interleaved SAR ADC with low-complexity background timing skew calibration
2. A 24–72-GS/s 8-b Time-Interleaved SAR ADC With 2.0–3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET
3. A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique
4. A 0.19 mm2 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS
5. A 56-GS/s 8-bit Time-Interleaved ADC With ENOB and BW Enhancement Techniques in 28-nm CMOS
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