Evaluation of Threshold Frequencies for Logic Single-Event Upsets at Bulk FinFET Technology Nodes
Author:
Affiliation:
1. Department of Electrical and Computer Engineering (ECE), Vanderbilt University, Nashville, TN, USA
2. Digital IPs Solution Division, Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan
3. Cisco Systems Inc., San Jose, CA, USA
Funder
Soft Error Consortium
U.S. Department of Energy National Nuclear Security Administration for Program support from the Stewardship Graduate Fellowship
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
https://ieeexplore.ieee.org/ielam/23/10638256/10433753-aam.pdf
Reference31 articles.
1. Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance
2. Single Event Transients in Digital CMOS—A Review
3. Modeling the effect of technology trends on the soft error rate of combinational logic
4. New methods for evaluating the impact of single event transients in VDSM ICs
5. On latching probability of particle induced transients in combinational networks
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