Design and Test of a Time-to-Digital Converter ASIC Based on a Differential Delay Line-Reference-Cited by-同舟云学术

Design and Test of a Time-to-Digital Converter ASIC Based on a Differential Delay Line

Published:2024-08 Issue:8 Volume:71 Page:2020-2025
ISSN:0018-9499
Container-title:IEEE Transactions on Nuclear Science
language:
Short-container-title:IEEE Trans. Nucl. Sci.

Author:

Gao Jie¹,Yang Dong-Xu¹,Wang Jian¹^ORCID,Qu Wen-Qing¹,Jiang Wei-Jie¹,Feng Yi¹^ORCID,Wang Zhi-Yue¹,Zhang Hong-Fei¹^ORCID

Affiliation:

1. Department of Modern Physics, State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, China

Funder

Fundamental Research Funds for the Central Universities

National Natural Science Foundation of China

Research Funds of the State Key Laboratory of Particle Detection and Electronics

Frontier Scientific Research Program of Deep Space Exploration Laboratory

Strategic Priority Research Program of CAS

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/23/10638189/10530160.pdf?arnumber=10530160

Reference17 articles.

1. A Multi-Chain Merged Tapped Delay Line for High Precision Time-to-Digital Converters in FPGAs

2. Bubble-Proof Algorithm for Wave Union TDCs

3. A 20-ps Time-to-Digital Converter (TDC) Implemented in Field-Programmable Gate Array (FPGA) with Automatic Temperature Correction

4. High resolution time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) with compensated process voltage and temperature (PVT) variations

5. An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

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