A Dithered-Digital-Mixing Background Timing-Skew Calibration Method for Time-Interleaved ADCs-Reference-Cited by-同舟云学术

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A Dithered-Digital-Mixing Background Timing-Skew Calibration Method for Time-Interleaved ADCs

Published:2024-05-19 Issue: Volume: Page:1-5
ISSN:
Container-title:2024 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Tao Yunsong¹,Zhong Yi¹,Shao Jin²,Men Changyou³,Jie Lu⁴,Sun Nan¹

Affiliation:

1. Tsinghua University,Department of Electronic Engineering,Beijing,China

2. Beijing Smartchip Microelectronics Technology Co., Ltd,Beijing,China

3. Hangzhou Vango Technologies, Inc.,Hangzhou,China

4. Tsinghua University,School of Integrated Circuits,Beijing,China

Funder

Beijing Innovation Center for Future Chip

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558642.pdf?arnumber=10558642

Reference10 articles.

1. A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC

2. A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration

3. A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS

4. A Fast Converging Correlation-Based Background Timing Skew Calibration Technique by Digital Windowing for Time-Interleaved ADCs

5. A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC

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