A Scalable and PVT Invariant Spiking Neuron Using Asynchronous CMOS Logic
Author:
Affiliation:
1. Carlos III University of Madrid,Electronic Tech. Dept.,Leganes,Spain
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10557746/10557828/10558397.pdf?arnumber=10558397
Reference11 articles.
1. A Phase-Encoded Voice Features Extraction Circuit Using Digital Mixers and Analog Filters based on Ring Oscillators
2. SPAIC: A sub-μW/Channel, 16-Channel General-Purpose Event-Based Analog Front-End with Dual-Mode Encoders
3. Always-On, Sub-300-nW, Event-Driven Spiking Neural Network based on Spike-Driven Clock-Generation and Clock- and Power-Gating for an Ultra-Low-Power Intelligent Device
4. Validation of a CMOS SNN network based on a time-domain threshold neuron circuit achieving 114.90 pJ/inference on MNIST
5. A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses With Spike-Timing Dependent Plasticity
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