Data Cache design considerations for the Itanium/sub /spl reg// 2 Processor-Reference-Cited by-同舟云学术

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Data Cache design considerations for the Itanium/sub /spl reg// 2 Processor

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Container-title:Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors
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Author:

Lyon T.,Delano E.,McNairy C.,Mulla D.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/8166/24311/01106794.pdf?arnumber=1106794

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Application Characteristics-Aware Sporadic Cache Bypassing for high performance GPGPUs;Journal of Parallel and Distributed Computing;2018-12

2. Early miss prediction based periodic cache bypassing for high performance GPUs;Microprocessors and Microsystems;2017-11

3. A Modified PSO Algorithm Based on Cache Replacement Algorithm;2014 Tenth International Conference on Computational Intelligence and Security;2014-11

4. Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2014-02

5. An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2013-01

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