Vector-Qubit models for SoC Logic-Structure Testing and Fault Simulation
Author:
Affiliation:
1. Kharkov National University of Radio Electronics,Design Automation Department,Kharkov,Ukraine
2. University of Missouri-Kansas,City,MO,USA
3. Azerbaijan State Oil and Industry University,Computer Engineering Department,Baku,Azerbaijan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9385168/9385208/09385266.pdf?arnumber=9385266
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. In-Memory Fault as Address Simulation;2023 IEEE East-West Design & Test Symposium (EWDTS);2023-09-22
2. VECTOR-LOGICAL FAULT SIMULATION;Radio Electronics, Computer Science, Control;2023-06-29
3. Vector Models for Modeling Logic Based on XOR-Relations;2022 IEEE 16th International Conference on Advanced Trends in Radioelectronics, Telecommunications and Computer Engineering (TCSET);2022-02-22
4. ДЕДУКТИВНЫЙ АНАЛИЗ ВЕКТОРНЫХ МОДЕЛЕЙ ЛОГИЧЕСКИХ ФУНКЦИЙ И СОЦИАЛЬНЫХ ОТНОШЕНИЙ;Proceedings;2022
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