Physical Design, Power and Area Optimization of High Frequency Block at Smaller Technology Node-Reference-Cited by-同舟云学术

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Physical Design, Power and Area Optimization of High Frequency Block at Smaller Technology Node

Published:2019-05 Issue: Volume: Page:
ISSN:
Container-title:2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)
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Author:

G C Ajay Kumar,Subrahmanya K N,Ammikkallingal Sajeesh,Polisetti Sai Anudeep

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8977147/9016382/09016844.pdf?arnumber=9016844

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Physical Design Implementation of SoC Module with Performance Optimization;2023 7th International Conference on Computation System and Information Technology for Sustainable Solutions (CSITSS);2023-11-02

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