A Framework for Fault Tolerance in RISC-V-Reference-Cited by-同舟云学术

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A Framework for Fault Tolerance in RISC-V

Published:2022-09-12 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE Intl Conf on Dependable, Autonomic and Secure Computing, Intl Conf on Pervasive Intelligence and Computing, Intl Conf on Cloud and Big Data Computing, Intl Conf on Cyber Science and Technology Congress (DASC/PiCom/CBDCom/CyberSciTech)
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Author:

Dorflinger Alexander¹,Kleinbeck Benedikt¹,Albers Mark¹,Michalik Harald¹,Moya Martin¹

Affiliation:

1. Technische Universität Braunschweig,Institute of Computer and Network Engineering (IDA),Braunschweig,Germany

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9927523/9927699/09927800.pdf?arnumber=9927800

Reference31 articles.

1. SEU fault classification by fault injection for an FPGA in the space instrument SOPHI

2. SHAKTI-F: A Fault Tolerant Microprocessor Architecture

3. Towards a fault tolerant RISC-V softcore;heida;Master Thesis TU Delft,2016

4. A fault tolerant memory architecture for a RISC-V softcore;verhage;Master Thesis TU Delft,2016

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1. A Smart Autonomous E-Bike Fail-Safe System;EAI/Springer Innovations in Communication and Computing;2024

2. Follow-On Testing of the Xilinx Versal Prime;2023 IEEE Radiation Effects Data Workshop (REDW) (in conjunction with 2023 NSREC);2023-07

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