DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training
Author:
Affiliation:
1. Department of Electrical, Electronic and Information Engineering, University of Bologna, Bologna, Italy
2. IIS Integrated Systems Laboratory, ETH Zürich, Zürich, Switzerland
Funder
EU Horizon 2020 Research and Innovation through the European Pilot Project
WiPLASH
ECSEL Horizon 2020 Project AI4DI
GreenWaves Technologies
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/8782712/9733783/09903915.pdf?arnumber=9903915
Reference36 articles.
1. PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning
2. GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors
3. NEURA ghe
4. A transprecision floating-point platform for ultra-low power computing
5. Dustin: A 16-cores parallel ultra-low-power cluster with 2b-to-32b fully flexible bit-precision and vector Lockstep execution mode;ottavi;arXiv 2201 08656,2022
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