Thin Memory Chip Fabrication for Multi-stack Hybrid Bonding Applications

Author:

Sekhar V. N.1,Mishra Dileep Kumar1,Choong Chong Ser1,Rao Vempati Srinivasa1

Affiliation:

1. Institute of Microelectronics (IME), A*STAR (Agency for Science, Technology and Research),Singapore,138634

Publisher

IEEE

Reference12 articles.

1. Comprehensive Study on Advanced Chip on Wafer Hybrid Bonding with Copper/Polyimide Systems

2. Cu-SiO 2 Hybrid Bonding Yield Enhancement Through Cu Grain Enlargement;murugesan;2022 IEEE 72nd Electronic Components and Technology Conference (ECTC),0

3. Recess Effect Study and Process Optimization of Sub-10 μm Pitch Die-to-wafer Hybrid Bonding

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1. Process Challenges in Thin Wafers Fabrication with Double Side Hybrid Bond Pads for Chip Stacking;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Dielectric Stack Optimization for Die-level Warpage Reduction for Chip-to-Wafer Hybrid Bonding;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

3. Multi-Chip Stacked Memory Module Development using Chip to Wafer (C2W) Hybrid Bonding for Heterogeneous Integration Applications;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

4. Evaluation of Low Temperature Inorganic Dielectric Materials for Hybrid Bonding Applications;2023 IEEE 25th Electronics Packaging Technology Conference (EPTC);2023-12-05

5. Polymer Dielectric Materials Evaluation for Hybrid Bonding Applications;2023 IEEE 25th Electronics Packaging Technology Conference (EPTC);2023-12-05

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