Thin Memory Chip Fabrication for Multi-stack Hybrid Bonding Applications
Author:
Affiliation:
1. Institute of Microelectronics (IME), A*STAR (Agency for Science, Technology and Research),Singapore,138634
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10012686/10013085/10013147.pdf?arnumber=10013147
Reference12 articles.
1. Comprehensive Study on Advanced Chip on Wafer Hybrid Bonding with Copper/Polyimide Systems
2. Cu-SiO 2 Hybrid Bonding Yield Enhancement Through Cu Grain Enlargement;murugesan;2022 IEEE 72nd Electronic Components and Technology Conference (ECTC),0
3. Recess Effect Study and Process Optimization of Sub-10 μm Pitch Die-to-wafer Hybrid Bonding
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