Fault-tolerant Design of Power Edge Computing Processor Based on Full-hardware Dual-core Lockstep
Author:
Affiliation:
1. Digital Grid Research Institute,China Southern Power Grid,Guangzhou,China
2. Institute of VLSI Design, Zhejiang University,Hangzhou,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9712847/9712848/09712894.pdf?arnumber=9712894
Reference20 articles.
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2. 8Gy” or” ok, G.; Beszédes, B. Duplicated control unit based embedded fault-masking systems;2017 IEEE 15th International Symposium on Intelligent Systems and Informatics (SISY),0
3. A Reconfigurable Generic Dual-Core Architecture
4. Dual-lockstep microblaze-based embedded system for error detection and recovery with reconfiguration technique[C];hanafi;Complex Systems,2016
5. New Techniques for Improving the Performance of the Lockstep Architecture for SEEs Mitigation in FPGA Embedded Processors
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