A Digital Frequency Locked Loop With Minimum Computation Overhead for Heavily Distorted Single-Phase Grid Systems
Author:
Affiliation:
1. Department of Electrical Engineering, IIT Ropar, Rupnagar, Punjab, India
Funder
IIT Ropar under ISIRD Grant
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Instrumentation
Link
http://xplorestaging.ieee.org/ielx7/19/9717300/09750077.pdf?arnumber=9750077
Reference30 articles.
1. Advanced Grid Synchronization System for Power Converters under Unbalanced and Distorted Operating Conditions
2. Addressing DC Component in PLL and Notch Filter Algorithms
3. Multiresonant Frequency-Locked Loop for Grid Synchronization of Power Converters Under Distorted Grid Conditions
4. Modified Second-Order Generalized Integrators With Modified Frequency Locked Loop for Fast Harmonics Estimation of Distorted Single-Phase Signals
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