1. A 0.7 pf-to-10nf fully digital capacitance-to-digital converter using iterative delay-chain discharge;jung;2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers,2015
2. An oscillator collapse-based comparator with application in a 74.1 db sndr, 20ks/s 15b sar adc;shim;2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits),0
3. A fully synthesizable distributed and scalable all-digital ldo in 10nm cmos;bang;2020 IEEE International Solid-State Circuits Conference-(ISSCC),0
4. A self-calibrated 1.2-to-3.8 ghz 0.0052mm2 synthesized fractional-n mdll using a 2b time-period comparator in 22nm finfet cmos;kundu;2020 IEEE International Solid-State Circuits Conference-(ISSCC),0
5. A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS