Cache Memory Design for Single Bit Architecture for IoT Applications-Reference-Cited by-同舟云学术

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Cache Memory Design for Single Bit Architecture for IoT Applications

Published:2021-10-22 Issue: Volume: Page:
ISSN:
Container-title:2021 5th International Conference on Information Systems and Computer Networks (ISCON)
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Author:

Agrawal Reeya¹

Affiliation:

1. GLA University Mathura Research Scholar, NIT Patna,Department of CSE

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9702150/9702296/09702515.pdf?arnumber=9702515

Reference20 articles.

1. Low power, high-speed VLSI circuits in 16nm technology;sudhakar;AIP Conference Proceedings,0

2. Selective Operating Preamplifier Circuit for Low Voltage Static Random Access Memory;hanwool;Journal of IKEEE,2021

3. Design and Simulation of Power efficient SRAM;neha;2021 2nd International Conference for Emerging Technology (INCET),0

4. SRAMs;navneet;TFET Integrated Circuits,2021

5. Sensing Techniques;navneet;TFET Integrated Circuits,2021

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Cache Memory Design for Single Bit Architecture with Different Sense燗mplifiers;Computers, Materials & Continua;2022

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