A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications-Reference-Cited by-同舟云学术

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A novel Si-Tunnel FET based SRAM design for ultra low-power 0.3V VDD applications

Published:2010-01 Issue: Volume: Page:
ISSN:
Container-title:2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
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Author:

Singh J.,Ramakrishnan K.,Mookerjea S.,Datta S.,Vijaykrishnan N.,Pradhan D.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5415928/5419673/05419897.pdf?arnumber=5419897

Cited by 33 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Capacitance Modeling With Charge Partitions Covering Full-Region Operations of TFETs;IEEE Transactions on Electron Devices;2024-07

2. Silicon cross-coupled gated tunneling diodes;Chip;2024-06

3. Design and Analysis of Si/GaSb HTFET-Based 7T SRAM Cell for Ultra-Low Voltage Applications;Silicon;2024-01-09

4. Mathematical Modeling of TFET and Its Future Applications;Advanced Ultra Low‐Power Semiconductor Devices;2023-10-27

5. State of the Art Tunnel FETs for Low Power Memory Applications;Advanced Ultra Low‐Power Semiconductor Devices;2023-10-27

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