Author:
Chu Zhufei,Soeken Mathias,Xia Yinshui,De Micheli Giovanni
Cited by
8 articles.
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1. Logic Synthesis;FPGA EDA;2024
2. Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
3. A Versatile Mapping Approach for Technology Mapping and Graph Optimization;2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC);2022-01-17
4. Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition;2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS);2021-04-07
5. Advanced Functional Decomposition Using Majority and Its Applications;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-08