Author:
Lai Jin-Yang,Chen Chiung-An,Chen Shih-Lun,Su Chun-Yu
Cited by
5 articles.
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2. Area and Speed-Efficient Floating-Point Arithmetic Logical Unit Implementation on FPGA;2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT);2024-04-06
3. Area And Speed-Efficient Vedic RISC Processors for Embedded Systems;2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT);2024-04-06
4. A Low-power CNN Processor for Edge Devices Based on Tight Coupling of CPU and Accelerator;2023 3rd International Conference on Electronic Information Engineering and Computer Science (EIECS);2023-09-22
5. RISC-V processor-based automatic access floating-point computing accelerated dataflow co-processor;2022 4th International Academic Exchange Conference on Science and Technology Innovation (IAECST);2022-12-09