BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis-Reference-Cited by-同舟云学术

BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis

Published:2024-02 Issue:2 Volume:43 Page:417-430
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Gu Tianchen¹^ORCID,Li Wangzhen¹^ORCID,Zhao Aidong¹,Bi Zhaori¹^ORCID,Li Xudong²,Yang Fan¹^ORCID,Yan Changhao¹^ORCID,Hu Wenchuang³,Zhou Dian⁴^ORCID,Cui Tao⁵^ORCID,Liu Xin⁵^ORCID,Zhang Zaikun⁶,Zeng Xuan¹^ORCID

Affiliation:

1. School of Microelectronics, State Key Laboratory of Integrated Chips and System, Fudan University, Shanghai, China

2. School of Data Science, Fudan University, Shanghai, China

3. Precision Medicine Center of West China Hospital, Sichuan University, Chengdu, China

4. Department of Electrical Engineering, University of Texas at Dallas, Dallas, TX, USA

5. Academy of Mathematics and Systems Science, Chinese Academy of Sciences, Beijing, China

6. Department of Applied Mathematics and the CAS AMSS-PolyU Joint Laboratory of Applied Mathematics, The Hong Kong Polytechnic University, Hong Kong, China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China (NSFC) research projects

Beijing Natural Science Foundation

Hong Kong RGC

Shanghai Science and Technology Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/10410112/10247570.pdf?arnumber=10247570