Author:
Radhika ,Pandey Neeta,Gupta Kirti,Gupta Maneesha
Cited by
8 articles.
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1. A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18
2. MOS Current Mode Logic (MCML) based techniques for D-Flip Flop in 180 nm Technology using LTspice;2023 2nd Edition of IEEE Delhi Section Flagship Conference (DELCON);2023-02-24
3. Design of MCML Based Logic for Low Power Digital Communication Application;2022 International Conference on Disruptive Technologies for Multi-Disciplinary Research and Applications (CENTCON);2022-12-22
4. Design of Current Mode MOS Logic for Low-Power Digital Applications;Lecture Notes in Electrical Engineering;2021
5. Tri-state CML Circuits;Model and Design of Improved Current Mode Logic Gates;2019-11-23