Low-Power Optimization Design of CMOS Phase-Locked Loop for WiFi-6E Applications
Author:
Affiliation:
1. Yuan Ze University,Dept. of Electrical Engineering,Taoyuan City,Taiwan
2. National Taipei University,Dept. of Electrical Engineering,New Taipei City,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9868970/9868972/09869131.pdf?arnumber=9869131
Reference5 articles.
1. A 0.6–4.2 V low-power configurable PLL architecture for 6 GHz-300MHz applications in a 90 nm CMOS process;raha;Proc Symp VLSI Circuits,0
2. A low-power quadrature VCO and its application to a 0.6-V 2.4-GHz PLL;lu;IEEE Trans Circuits Syst I,2010
3. A 5-GHz Adjustable Loop Bandwidth Frequency Synthesizer With an On-Chip Loop Filter Array
4. A 0.5-V 1.9-GHz Low-Power Phase-Locked Loop in 0.18-¿m CMOS
5. A 0.5-V, 440-µW Frequency Synthesizer for Implantable Medical Devices
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