On-Chip High-Resolution Timing Characterization Circuits for Memory IPs-Reference-Cited by-同舟云学术

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On-Chip High-Resolution Timing Characterization Circuits for Memory IPs

Published:2022-09-19 Issue: Volume: Page:
ISSN:
Container-title:ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)
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Author:

Agarwal Amit¹,Hsu Steven¹,Anders Mark¹,Pandya Gunjan²,Krishnamurthy Ram¹,Tschanz James¹,De Vivek¹

Affiliation:

1. Intel Corporation,Circuits Research Lab, Intel Labs,Hillsboro,OR,97124

2. Corporate Memory Organization, Intel Corporation,Hillsboro,OR,97124

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9911257/9911222/09911374.pdf?arnumber=9911374

Reference7 articles.

1. A 32nm 8.3GHz 64-entry × 32b variation tolerant near-threshold voltage register file

2. Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing

3. Self-Calibrate two-step digital setup/hold time measurement

4. 25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS

5. A test circuit for measurement of clocked storage element characteristics

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Single Ring-Oscillator-Based Test Structure for Timing Characterization of Dynamic Circuit;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-05

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