A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW
Author:
Affiliation:
1. NXP Semiconductors,Eindhoven,the Netherlands
2. NXP Semiconductors,Hamburg,Germany
3. NXP Semiconductors,Nijmegen,the Netherlands
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9911257/9911222/09911312.pdf?arnumber=9911312
Reference7 articles.
1. A 2.2 GHz Continuous-Time $\mathrm {\Delta \!\Sigma }$ ADC With −102 dBc THD and 25 MHz Bandwidth
2. Design Techniques for High-Resolution Continuous-Time Delta–Sigma Converters With Low In-Band Noise Spectral Density
3. Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta–Sigma Modulator
4. A 28nm 6GHz 2b Continuous-Time $\Delta\Sigma$ ADC with −101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction
5. A 134-μW 99.4-dB SNDR Audio Continuous-Time Delta-Sigma Modulator With Chopped Negative-R and Tri-Level FIR-DAC
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1. A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme;IEEE Journal of Solid-State Circuits;2024-04
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