Ultra-Thinning of 20 nm-Node DRAMs down to 3 µm for Wafer-on-Wafer (WOW) Applications

Author:

Chen Zhiwen,Araki Naoko,Kim Youngsuk,Fukuda Tadashi,Sakui Koji,Nakamura Tomoji,Kobayashi Tatsuji,Obara Takashi,Ohba Takayuki

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Novel Single and Co-Ion Implantation Induced Backside Etch Stop Structures for 3D Multilayer Stacked Package;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Minimizing die fracture in 3DIC die integration;Journal of Micro/Nanopatterning, Materials, and Metrology;2024-01-02

3. FEA Simulations for Thermal Distributions of Large Scale 3DIC Packages;IEEE Access;2024

4. Electrical and Thermal Analysis of Bumpless Build Cube 3D Using Wafer-on-Wafer and Chip-on-Wafer for Near Memory Computing;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05

5. Raman Spectroscopy and Hyperspectral Imaging for Wafer-On-Wafer (WOW) Processing;2022 17th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT);2022-10-26

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