A 6-ns 1-Mb CMOS SRAM with latched sense amplifier-Reference-Cited by-同舟云学术

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A 6-ns 1-Mb CMOS SRAM with latched sense amplifier

Published:1993-04 Issue:4 Volume:28 Page:478-483
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Seki T.,Itoh E.,Furukawa C.,Maeno I.,Ozawa T.,Sano H.,Suzuki N.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx1/4/5447/00210031.pdf?arnumber=210031

Cited by 26 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A latch-based sense amplifier with improved performance for single ended SRAM application;Physica Scripta;2023-05-30

2. Design of Low Power PMOS Biased Sense Amplifier Using Lector Approach;2022 IEEE International Conference on Semiconductor Electronics (ICSE);2022-08-15

3. Low Power, High Performance PMOS Biased Sense Amplifier;2021 12th International Symposium on Advanced Topics in Electrical Engineering (ATEE);2021-03-25

4. Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology;Microelectronics Journal;2014-01

5. Review of Sense Amplifiers for Static Random Access Memory;IETE Technical Review;2013

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