Polarity and Patterning Effect on Plasma Charging Levels by Metal-Gate Coupled Recorder Arrays
Author:
Affiliation:
1. Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9967813/09928276.pdf?arnumber=9928276
Reference21 articles.
1. Plasma induced damage of aggressively scaled gate dielectric (EOT ? 1.0 nm) in metal gate/high-k dielectric CMOSFETs;min;Proc IEEE Int Rel Phys Symp (IRPS),2008
2. New applications and challenges of dielectric films at 14 nm FinFET technology and beyond;deng;Proc IEEE China Semicond Technol Int Conf (CSTIC),2016
3. A Comprehensive Model for Plasma Damage Enhanced Transistor Reliability Degradation
4. Wafer-Level Mapping of Plasma-Induced Charging Effect by On-Chip In Situ Recorders in FinFET Technologies
5. Plasma Charge Accumulative Model in Quantitative FinFET Plasma Damage
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