A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes-Reference-Cited by-同舟云学术

A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes

Published:2022-08 Issue:8 Volume:69 Page:4453-4459
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Nibhanupudi S. S. Teja¹^ORCID,Prasad Divya²^ORCID,Das Shidhartha²^ORCID,Zografos Odysseas³,Robinson Alex²,Gupta Anshul³^ORCID,Spessot Alessio³^ORCID,Debacker Peter³^ORCID,Verkest Diederik³,Ryckaert Julien³,Hellings Geert³^ORCID,Myers James²,Cline Brian²,Kulkarni Jaydeep P.¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA

2. ARM Research, Austin, TX, USA

3. imec, Leuven, Belgium

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9839401/09817394.pdf?arnumber=9817394

Reference19 articles.

1. Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration

2. Enabling logic with backside connectivity via n-TSVs and its potential as a scaling booster;veloso;Proc Symp VLSI Technol,2021

3. DTCO exploration for efficient standard cell power rails;chava;Proc SPIE,2018

4. External I/O interfaces in sub-5 nm GAA NS technology and STCO scaling options;chen;Proc Symp VLSI Technol,2021

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2. Solving the Annealing of Mo Interconnects for Next‐Gen Integrated Circuits;Advanced Electronic Materials;2024-06-24

3. System Level Analysis and Design Optimization of Back-side Power Delivery Network for Advanced Nodes;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

4. High-density standard cell libraries with backside power options in A14 nanosheet node;DTCO and Computational Patterning III;2024-04-10

5. Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop Reduction;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25