Recessed Channel Ferroelectric-Gate Field-Effect Transistor Memory With Ferroelectric Layer Between Dual Metal Gates-Reference-Cited by-同舟云学术

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Recessed Channel Ferroelectric-Gate Field-Effect Transistor Memory With Ferroelectric Layer Between Dual Metal Gates

Published:2022-03 Issue:3 Volume:69 Page:1054-1057
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Kwak Been¹^ORCID,Lee Kitae²^ORCID,Park Noh-Hwal³,Jeon Seung Joon³,Kim Hyunwoo⁴^ORCID,Kwon Daewoong¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Inha University, Incheon, South Korea

2. Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea

3. 3-D Convergence Center, Inha University, Incheon, South Korea

4. School of Electronic and Electrical Engineering, Hankyong National University, Anseong, South Korea

Funder

Brain Korea 21 Four Program

Future Semiconductor Device Technology Development Program

Ministry of Trade, Industry and Energy (MOTIE) and Korea Semiconductor Research Consortium

National Research Foundation

Korean Ministry of Science and ICT

Samsung Electronics Company Ltd.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9722602/09709495.pdf?arnumber=9709495

Reference18 articles.

1. A Novel Dual Ferroelectric Layer Based MFMFIS FeFET with Optimal Stack Tuning toward Low Power and High-Speed NVM for Neuromorphic Applications

2. Reduction of GIDL Using Dual Work-Function Metal Gate in DRAM

3. Improvement of Row Hammering Using Metal Nanoparticles in DRAM—A Simulation Study

4. Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors

5. Low Voltage Operation of Nonvolatile Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS)-Field-Effect-Transistors (FETs) Using Pt/SrBi2Ta2O9/Pt/SrTa2O6/SiON/Si Structures

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. TCAD simulation study of dual ferroelectric gate field-effect transistors with a recessed channel geometry for non-volatile memory applications;Journal of the Korean Physical Society;2024-05-16

2. Suppression of Gate-Induced-Drain-Leakage Utilizing Local Polarization in Ferroelectric-Gate Field-Effect Transistors for DRAM Applications;IEEE Electron Device Letters;2024-05

3. Effects of Deposition Power and Thermal Treatment on Ferroelectric Properties of Sputtered Hf₀.₅Zr₀.₅O₂;IEEE Transactions on Electron Devices;2024-05

4. Signal-Processing Application Based on Ferroelectric Tunnel Field-Effect Transistor;IEEE Transactions on Nanotechnology;2024

5. Ferroelectric Field Effect Transistors (FeFETs): Advancements, challenges and exciting prospects for next generation Non-Volatile Memory (NVM) applications;Materials Today Communications;2023-06

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