Optimized Design Implementation and Research of SM3 Hash Algorithm Based on FPGA-Reference-Cited by-同舟云学术

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Optimized Design Implementation and Research of SM3 Hash Algorithm Based on FPGA

Published:2022-10 Issue: Volume: Page:
ISSN:
Container-title:2022 2nd International Conference on Computer Science and Blockchain (CCSB)
language:
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Author:

Xu Yingpeng¹,Han Lin²,Yu Zhe²,Che Fang²

Affiliation:

1. The Frontier Information Technology Research Institute, Zhongyuan University of Technology,Zhengzhou,China

2. Nation Supercomputing Center in Zhengzhou, Zhengzhou University,Zhengzhou,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10071526/10071567/10071574.pdf?arnumber=10071574

Reference22 articles.

1. Implementation and application of SM3 algorithm in hardware encryption module;zhang;Information and Communication,2019

2. Design and Implementation of SM3 Algorithm in ASIC;zhang;Microelectronics & Computer,2014

3. High speed ASIC design and implementation of SM3 algorithm;yu;Microelectronics & Computer,2016

4. Design and implementation of SM3 algorithm on FPGA;ding;Microcomputer & Its Applications,0

5. High-speed hardware design of SM3 algorithm based on double flow synchronous iteration;gu;Computer Networks,2020

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A CUDA-based parallel optimization method for SM3 hash algorithm;The Journal of Supercomputing;2024-06-10

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