Preliminary Study on Noise-Resilient Artificial Neural Networks for On-Chip Test Generation

Author:

Inamoto Tsutomu1,Nishino Tomoki2,Wang Senling1,Higami Yoshinobu1,Takahashi Hiroshi1

Affiliation:

1. Ehime University 3 Bunkyo, Matsuyama,Graduate School of Science and Engineering,Ehime,Japan,791-8577

2. INFOCOM WEST JAPAN CORPORATION 1-6-29 Kyutaro-machi, Chuo-ku,Osaka,Japan,541-0056

Publisher

IEEE

Reference12 articles.

1. Combinational profiles of sequential benchmark circuits

2. A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran;brglez;Proceedings of the IEEE Int’l Symposium Circuits and Systems (ISCAS ’85),1985

3. Generative adversarial nets;goodfellow;Advances in neural information processing systems,2014

4. Multiply accumulate operations in memristor crossbar arrays for analog computing

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